A semiconductor device wherein a lateral diffused MOS transistor element is formed at the surface layer part of a semiconductor substrate, and a method for manufacturing the semiconductor device are disclosed in, for example, JP-A-2001-352707, which corresponds to EP 1143598-A2.
FIG. 10 is a schematic sectional view of a semiconductor device 100 which is the semiconductor device disclosed in EP 1143598-A2. The semiconductor device 100 shown in FIG. 10 is formed on an SOI substrate which consists of a p-type silicon substrate 2, an insulating layer 3 and an n-type layer 1. In the semiconductor device 100, an n-type region 6 which is formed to be higher in concentration than the n-type layer 1 and whose concentration becomes higher at its position nearer to an n+-type drain region 5 is arranged so as to surround the n+-type drain region 5. Further, a p+-type contact region 9 which is arranged in adjacency to an n+-type source region 8 is formed so as to extend under the n+-type source region 8. By the way, in FIG. 10, numeral 4 designates a LOCOS oxide film, numeral 10 a gate insulating film, numeral 11 a gate electrode, numeral 12 an inter-layer insulating film, numeral 13 a source electrode, and numeral 14 a drain electrode.
The semiconductor device 100 shown in FIG. 10 is the semiconductor device formed with the lateral diffused MOS transistor element (LDMOS, Lateral Diffused Metal Oxide Semiconductor) in which a source and a drain are arranged at the surface layer part of the n-type layer 1, so that carriers flow in the lateral direction of the semiconductor substrate. Since the LDMOS is capable of high-speed switching as compared with any other transistor element, it is utilized in, for example, a switching circuit or a switching power source in which a transistor element is turned ON/OFF at high speed.
In general, in the switching circuit such as DC-DC converter or inverter, as the operating frequency of the circuit is heightened more, an accessory inductance or capacitance becomes smaller, so that the size of the circuit can be made smaller. For this purpose, a transistor element of highest possible switching speed is required. On the other hand, when a transistor element is switched at high speed, the overshoot of a drain voltage (surge voltage) arises due to the abrupt voltage change (dV/dt) of the transistor element. Accordingly, induced noise increases, and also a switching loss increases.
A semiconductor device which is intended to solve the above problem of the transistor element applied to the switching circuit is disclosed in JP-A-2004-6598, which corresponds to U.S. Pat. No. 6,700,156.
FIG. 11 is a schematic perspective view partially shown in sections, of a semiconductor device 90 which is the semiconductor device disclosed in U.S. Pat. No. 6,700,156. The semiconductor device 90 shown in FIG. 11 is a semiconductor device formed with a vertical diffused MOS transistor element (VDMOS, Vertical Diffused Metal Oxide Semiconductor) in which a source and a drain are arranged on both the sides of a semiconductor substrate, so that carriers flow in the vertical direction of the semiconductor substrate. This semiconductor device 90 of FIG. 11 features that a p-layer 14 which contains an impurity of p-conductivity type at a low concentration is disposed at a position adjoining a p-base layer 12.
In the semiconductor device 90 of FIG. 11, owing to the formation of the p-layer 14, a gate-drain capacitance can be enlarged more as a drain voltage becomes higher, thereby to suppress the appearance of a surge voltage at the drain. However, the formation of the p-layer 14 is effective only in the semiconductor device 90 having the VDMOS structure. When a similar p-layer 14 is formed in the semiconductor device having the LDMOS structure, the design of the LDMOS becomes difficult on account of great influence on a carrier flow path. Besides, in the semiconductor device 90, the carriers flow through the p-layer 14 of the low impurity concentration, and hence, an ON-resistance becomes high. Further, merely by the formation of the p-layer 14, the increase of the gate-drain capacitance is insufficient, and the effect of the suppressing the surge voltage is unsatisfactory.
Therefore, a new switching circuit K1 shown in FIG. 12 as a related art has been formed in order to avoid the problems of the transistor elements which are applied to the switching circuits.
The switching circuit K1 of FIG. 12 is a switching circuit in which, by changing-over the gate voltage of a transistor T5, the path between a drain D and a source S forming the main electrodes of the transistor T5 is temporally changed-over between a conductive state and a non-conductive state. In the switching circuit K1, the drain D and gate G of the transistor T5 are connected by a series circuit which consists of a Zener diode Dz and a capacitor C. Thus, while a drain voltage is low, the Zener diode Dz is not turned ON, to establish a state where the capacitance of the capacitor C does not contribute, so that a drain current and the drain voltage change at high speed to make a switching loss slight. On the other hand, when the drain voltage rises, the Zener diode Dz breaks down, and the capacitance of the capacitor C is added in the D-G path, so that the drain current and the drain voltage change at low speed to suppress a surge voltage to a low level. In the above way, the switching circuit K1 shown in FIG. 12 is the switching circuit which can simultaneously suppress both the switching loss and the surge voltage. Incidentally, regarding the invention of the switching circuit, a Japanese patent application No. 2006-86225 (i.e., U.S. patent application Ser. No. 11/723,967) has already been filed.
Thus, it is required to provide a semiconductor device which is well suited for the configuration of a switching circuit, and it is also required to provide a semiconductor device formed with a lateral diffused MOS transistor capable of high-speed switching, which semiconductor device can simultaneously suppress both a switching loss and a surge voltage (noise) and which is small in size and low in price.